1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same. More particularly, the present invention relates to a semiconductor device with a resistor and to a method of forming the same.
2. Description of the Related Arts
Polysilicon is often used as a resistor in a semiconductor device, since it is easy to control resistance by controlling the impurity doping concentration of the polysilicon. In many conventional non-volatile memory devices, resistors in a peripheral circuit region are formed as explained below.
FIG. 1 illustrates a plan view of a semiconductor device according to a conventional technology. FIG. 2 illustrates cross-sectional views taken along the I-I′ line and the II-II′ line of FIG. 1, respectively.
Referring to FIGS. 1 and 2, a field oxide (FOX) 32 is formed on a semiconductor substrate 31, which is divided into a cell array region “a” and a peripheral circuit region “b,” thereby defining an active region (AR). A tunnel oxide layer 33, a charge trapping layer 35, a blocking insulation layer 37, a polysilicon layer 39, and a tungsten silicide layer 40 are sequentially stacked on the surface of the semiconductor substrate 31. The layers 40, 39, 37, 35, and 33 are sequentially patterned to form one string of word lines (WL) 41w that cross over the active region (AR) and are parallel to each other at the cell array region “a.” Simultaneously, a string selection line (SSL, not shown) and a ground selection line (GSL) 41g are formed at both sides of the one string of the world lines (WL) 41w, respectively. Also, a resistor (R) 41r is formed on the field oxide 32 at the peripheral circuit region “b” by a patterning process. After finishing the patterning process, impurities are implanted into the exposed active region (AR), thereby forming an impurity region (43). An interlayer dielectric layer 47 is stacked to cover the lines 41w and 41g and the resistor 41r. A common source line (CSL) 45 is formed through the interlayer dielectric layer 47 between a ground selection line 41g and a neighboring ground selection line 41g at the cell array region “a.” An additional interlayer dielectric layer is stacked on the common source line 45. The interlayer dielectric layer 47 is then penetrated to form a resistor contact (RC) 49, which electrically connects to the tungsten silicide layer 40 at the peripheral circuit region “b.” However, since the tungsten silicide layer 40 has a relatively very low sheet resistance in comparison with polysilicon, the area of the resistor is enlarged.
In order to solve the problem, as illustrated in FIG. 3, a method can be considered, which perfectly removes the tungsten silicide 40 in the peripheral circuit region “b.” However, when a dry etch process is performed to remove the tungsten silicide layer 40, an etch rate is difficult to control, which results in an uneven surface and an uneven (that is, non-constant) resistance of the resistor. Also, since a new mask is required for the dry etch, this results in a further complexity during the process. The tungsten silicide layer 40 is hardly ever removed by a wet etch because this method can easily damage the polysilicon layer 39 there under.